1. Field of the Invention
The present invention relates to a photoelectric conversion apparatus and an image capturing system.
2. Description of the Related Art
A so-called amplification type photoelectric conversion apparatus having the merits of user friendliness, low power consumption, and the like has been developed. In this amplification type photoelectric conversion apparatus, fixed pattern noise (to be referred to as FPN hereinafter) caused by threshold variations of amplification transistors for amplifying signals from the respective pixels mixes in an optical signal. Japanese Patent Laid-Open No. 2003-051989 therefore proposes a technique of suppressing FPN by using a readout circuit for performing correlation double sampling (to be referred to as CDS hereinafter) which computes the difference between an optical signal and a reset signal.
Japanese Patent Laid-Open No. 2003-051989 therefore proposes a technique of providing a column amplification unit for each column signal line, amplifying an optical signal and a reset signal by using each column amplification unit, and performing CDS processing for the amplified signals by using a readout circuit. This makes it possible to suppress FPN by effectively performing CDS processing.
In a photoelectric conversion apparatus 100 disclosed in Japanese Patent Laid-Open No. 2003-051989, in some cases, no light enters a pixel 1 on the right column of a 2×2 pixel array PA, and high-luminance light enters a pixel 1 on the left column of the array, as shown in FIG. 7. At this time, the amount of electric charge (signal) stored in a photoelectric conversion unit 1a of the pixel 1 on the right column becomes zero, and the amount of electric charge (signal) stored in a photoelectric conversion unit 1a of the pixel 1 on the left column becomes large. The signal output from the pixel 1 on the right column to a column amplification unit (column amplifier) 106 via a first column signal line L101 becomes almost zero. In contrast, the signal output from the pixel 1 on the left column to a column amplification unit 106 via a first column signal line L101 becomes a large value.
As shown in FIG. 8, in the column amplification unit 106 for the pixel 1 on the right column, the zero signal is input from the pixel 1 to an input terminal 26 via the first column signal line L101 and a capacitor 33, and a reference signal (reference voltage Vref) is input to an input terminal 25. A differential amplifier 24 amplifies the difference between the two signals. The differential signal generated by amplifying the difference is input to an output buffer unit 28 functioning as a source follower. The output buffer unit 28 outputs a signal corresponding to the differential signal from an output terminal 29 to a second column signal line L102. At this time, no large current (excessive current) flows between the drain and source of a transistor Tr of the output buffer unit 28.
In contrast, as shown in FIG. 8, in the column amplification unit 106 for the pixel 1 on the left column, a high-level signal is input from the pixel 1 to the input terminal 26 via the first column signal line L101, and a reference signal (reference voltage Vref) is input to the input terminal 25. The differential amplifier 24 amplifies the difference between the two signals. The differential signal generated by amplifying the difference is input to the output buffer unit 28 functioning as a source follower. The output buffer unit 28 outputs a signal corresponding to the differential signal from the output terminal 29 to the second column signal line L102. At this time, the load of a current for charging holding capacitors 7 and 8 of a readout circuit 5 electrically connected to the second column signal line L102 increases, and hence a large current (excessive current) flows between the drain and source of the transistor Tr of the output buffer unit 28. As a consequence, a large current (excessive current) also flows in a power supply line L103.
With this operation, as shown in FIG. 9, the interconnection resistance of the power supply line L103 temporarily decreases the potential of the power supply line L103 at a timing T1 at which the holding capacitors 7 and 8 of the readout circuit 5 electrically connected to the second column signal line L102 start charging up. At a timing T2 at which the holding capacitors 7 and 8 finish charging up, the potential of the power supply line L103 is still lower than a potential VDD. Note that the potential VDD is the power supply potential of a supply source.
The column amplification unit 106 on the right column shares the power supply line L103 with the column amplification unit 106 on the left column (see FIG. 7), and hence outputs a signal different from a zero signal, which should output a zero signal, due to the influence of the temporal potential variation of the power supply line L103.
In an image corresponding to the image signal obtained in this manner, as shown in FIG. 10, an alias (horizontal smear) occurs in an area 45 horizontally adjacent to a high-brightness object 40.